1. Field of the Invention
The present invention relates to the field of signal processing in a channel, and in particular, to signal processing in a magnetic recording channel.
2. Background Art
In magnetic recording devices, such as magnetic disks and tapes, a recording head is used to read and write information to and from a magnetic surface. In a typical rotating medium-based storage system, data is stored on magnetic disks in a series of concentric "tracks." These tracks are accessed by a read/write head that detects variations in the magnetic orientation of the disk surface. The read/write head moves back and forth radially on the disk under control of a head-positioning servo mechanism so that it can be selectively positioned over a selected one of the tracks. Once in position over a track, the servo mechanism causes the head to trace a path that follows the center line of the selected track.
Generally, the inductive recording head consists of a slit toroid made up of high permeability magnetic material and wound by several conductor turns. The toroid contains a gap which is positioned over the data tracks on the magnetic recording surface. To record, a current is generated through the conductor windings, altering the magnetic field in the toroid. At the location of the gap, the amplitude of the magnetic field is large enough to record on the magnetic material of the storage device to a sufficient depth. The amplitude of the magnetic field falls off sharply away from the gap. By manipulating the current through the conductor windings, the magnitude and direction of the magnetic flux at the location of the gap can be modulated in such a fashion as to encode information into the magnetic surface of the storage device. A pattern of external and internal fields are created as the head and recording surface are moved relative to each other. These patterns are similar to a series of bar magnets of changing polarities. The polarity transitions are then readable as transitions in the magnetic flux at the recording surface. In read mode, as the magnetic storage surface moves across the gap in the head, the magnetic field of the storage surface is detected at the gap, and a voltage is induced in the coil proportional to the rate of change of the flux. The read channel then processes this analog voltage signal to obtain the digital data.
Magnetic storage devices sometimes use analog peak detection to process incoming read signals. However, as recording density increases, the analog peak detection scheme becomes unreliable because of the large amount of inter-symbol interference (ISI) between adjacent pulses. Alternatively, a partial response maximum likelihood (PRML) channel can be used to increase the recording density. However, this method requires very good equalization of the read signal and the code is completely incompatible with the currently widely used (1,7) run-length limited (RLL) code. More importantly, the required number of magnetic flux transitions per inch is 50 percent higher than that of the (1,7) code at the same density. Therefore, the magnetic non-linearity problem is more severe for the PRML system, and could even render it unusable at high recording densities.
Run-length limited (RLL) codes are useful because they place an upper bound on the number of clock cycles occurring between transitions. Because clock recovery is based on the occurrence of these transitions, this upper bound is very important. For example, a long train of "0's " in a data sequence produces no transitions and the clock recovery circuit has no input pulse with which to synchronize its tracking. In this situation, the data recovery timing might drift out of phase. For this reason, RLL codes are used to insure that sufficient transitions occur for the clock recovery circuit to maintain the correct timing phase and frequency. The (1,7) RLL code is characterized by a minimum of one "0" and a maximum of seven "0's" between consecutive "1's". In an NRZI format, where each "1" is represented by a transition, and each "0" is represented by the lack of a transition, the (1,7) RLL code is sufficient for clock recovery purposes. Also, by maintaining the minimum of one "0" between consecutive "1's", transitions are separated so as to be differentiable from one another.
It is desirable to have a signal processing method that uses RLL codes and can still improve the detection margin at high recording densities. In A.M. Patel's article "A New Digital Signal Processing Channel for Data Storage Products," in Digest of the Magnetic Recording Conference, of June 1991, pp. E6-E7, and in U.S. Pat. No. 4,945,538 issued to Patel, a (1,7) ML channel is described that is intended to achieve these goals.
A block diagram of the channel described by Patel is illustrated in FIG. 1. The analog read signal, originating from the read head, is amplified in preamplifier (preamp) 111 and then provided to filter 112 for the removal of high-frequency noise components. The filtered signal is then provided to phase-locked loop clock circuit 113 and delay line 114. Delay line 114 provides the delayed signal to analog-to-digital converter (ADC) 115 where the signal is digitized. The digitized signal is passed through equalizer 116 to obtain a more desirable waveform, and the result is provided to decoder 118. Decoder 118 implements a decoding algorithm to generate the digital data signal 119. The analog-to-digital converter 115 and decoder 118 are clocked by a clock signal 117 generated in phase-locked loop clock circuit 113.
There are several drawbacks to the (1,7) ML channel. It is difficult, to derive the read clock directly from the sample data. Patel mentions that a conventional peak detection channel is used to provide timing reference for the phase-lock loop, and an adjustable delay line is needed to cancel the timing mismatch between the peak detection channel and the (1, 7) ML channel. Due to the open loop characteristics of this approach, this method is unable to obtain very precise timing recovery. Also, delay lines are costly and unsuitable for monolithic integrated circuit implementation. Another disadvantage is the decoding functions involve five sample values and, therefore, are sensitive to mis-equalization because errors will accumulate in certain data patterns.
With a large number of sample values involved in the decoding operations of a channel, a strict requirement is placed on the equalizer. Because the decoding functions serve to match the sample values against an expected waveform, the equalizer must force the signal to conform to this expected shape. With a smaller amount of sample values involved, the constraints placed on the equalizer are less stringent and are thus more likely to be physically realizable.
FIG. 7A depicts the peak detection clock recovery circuit of the prior art. Input signal 700 represents the output of filter 112 from FIG. 1. Input signal 700 is provided to block 701 wherein its derivative with respect to time is generated as signal 702. However, circuits for generating this derivative are noisy. Therefore, a noise error model is included in FIG. 7A comprising noise signal 703 added to the derivative 702 in adder 704. The resulting signal 705, with the noise superimposed on the derivative signal, is provided to a zero crossing detector 706. Ideally, when the input signal 700 reaches a positive or negative peak, the derivative input to the zero crossing detector will be exactly zero, and the output of the detector, signal 707, will be "1". However, in physical realizations, the noise in signal 705 will cause the actual zero occurrence to be misaligned by the magnitude of the noise error.
Block 708 comprises threshold compactors for indicating whether the input signal 700 has reached a minimum qualifying threshold. When the signal is above a certain positive threshold, or below a certain negative threshold, signal 709 will be asserted. AND gate 710 will output a "1" on line 711 only if both signals 707 and 709 are asserted. The presence of the threshold comparators 708 insures that local peaks caused by noise in signal 700 are not mistakenly interpreted as signal transitions. The assertion of signal 711 signifies a peak. This "peak detected" signal is provided to a standard phase-locked loop 712 comprising a phase detector 731 for receiving signal 711, a loop filter 732 for filtering the output of phase detector 731, and a voltage-controlled oscillator 733 (VCO) controlled by the output of the filter and connected in feedback to the phase detector. The output 117 of the VCO is the clock signal for the system.